bit - VHDL: std_logic_vector Leftshift and right shift operator? -

how peform rightshift or left shift in vhdl on std_logic_vector...

it not work , why??`

an <= "0001";         counterprocess: process(clk,switch)     begin     if rising_edge(clk)         if prescaler < limit              prescaler <= prescaler + 1;             else                 prescaler <= (others => '0');                  counter <= counter + 1;                 sll 1;         end if;     end if;      end process;     <= anode;      segment <= counter;       end behavioral; 

i error message: sll can not have such operands in context. in context can used in, , how can perform left shift?

these includes:

    library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; 

isn't 1 needed perform leftshift operations included??

---

complete code

entity main port(         clk: in std_logic;         led: out std_logic_vector (7 downto 0);         switch: in std_logic_vector(7 downto 0);         segment: out std_logic_vector (7 downto 0);          an: out std_logic_vector (3 downto 0)          );  end main;   architecture behavioral of main signal counter: std_logic_vector (7 downto 0); signal prescaler:  std_logic_vector(25 downto 0); signal limit: std_logic_vector (25 downto 0); signal anode: std_logic_vector (3 downto 0); begin <= "0001";  scalerchoice: process(switch) begin case switch when "00000001" => limit <= "10111110101111000010000000"; -- 1 hz; when "00000010" => limit <= "00111111100101000000101011"; -- 3 hz when "00000100" => limit <= "00010011000100101101000000"; -- 10 hz when "00001000" => limit <= "00000111101000010010000000"; -- 25 hz when "00010000" => limit <= "00000011110100001001000000"; -- 50 hz;  when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz when others => limit <=      "00000000000000000000000001"; -- 50 mhz end case; end process;   counterprocess: process(clk,switch) begin if rising_edge(clk)     if prescaler < limit          prescaler <= prescaler + 1;         else             prescaler <= (others => '0');              counter <= counter + 1;             sll 1;     end if; end if;  end process;  segment <= counter;   end behavioral; 

edit 1:

your code edited reset logic, notice addition of reset signal ports list, deletion of asynchronous line setting value, addition of reset sensitivity list of counterprocess process, addition of if(reset = '1') line, , change of if elsif, change of shifting line:

i don't know an <= anode line doing, , believe in error also.

entity main port(     reset:   in  std_logic;     clk:     in  std_logic;     led:     out std_logic_vector(7 downto 0);     switch:  in  std_logic_vector(7 downto 0);     segment: out std_logic_vector(7 downto 0);      an:      out std_logic_vector(3 downto 0) ); end main;  architecture behavioral of main signal counter:   std_logic_vector(7  downto 0); signal prescaler: std_logic_vector(25 downto 0); signal limit:     std_logic_vector(25 downto 0); signal anode:     std_logic_vector(3  downto 0);  begin  scalerchoice: process(switch) begin case switch when "00000001" => limit <= "10111110101111000010000000"; -- 1 hz; when "00000010" => limit <= "00111111100101000000101011"; -- 3 hz when "00000100" => limit <= "00010011000100101101000000"; -- 10 hz when "00001000" => limit <= "00000111101000010010000000"; -- 25 hz when "00010000" => limit <= "00000011110100001001000000"; -- 50 hz;  when "00100000" => limit <= "00000001111010000100100000"; -- 100 hz when others => limit <=     "00000000000000000000000001"; -- 50 mhz end case; end process;   counterprocess: process(reset, clk, switch) begin     if(reset = '1')         <= "0001";     elsif rising_edge(clk)         if prescaler < limit              prescaler <= prescaler + 1;         else             prescaler <= (others => '0');              counter <= counter + 1;             <= std_logic_vector(unsigned(an) sll 1);         end if;     end if; end process;  <= anode; segment <= counter;   end behavioral; 

you need write line have:

an sll 1; 

as

an <= sll 1; 

remember an variable needs "set". line above

counter <= counter + 1;